Semiconductor Structure Including A Spatially Confined Dielectric Region

ABSTRACT

There are disclosed herein various implementations of semiconductor structures including one or more spatially confined dielectric regions. In one exemplary implementation, such a semiconductor structure includes a III-Nitride field-effect transistor (FET) having a drain, a source, and a gate, fabricated over a substrate. A spatially confined dielectric region is formed under the drain in the substrate, the spatially confined dielectric region reducing a capacitive coupling of the drain to the substrate. In another exemplary implementation, a spatially confined dielectric region is formed under each of the source and the drain of the FET, in the substrate, the spatially confined dielectric regions reducing a capacitive coupling of the source and the drain to the substrate.

The present application claims the benefit of and priority to aprovisional application entitled “III-Nitride Transistor IncludingSpatially Defined Buried Dielectric,” Ser. No. 61/752,258 filed on Jan.14, 2013. The disclosure in this pending provisional application ishereby incorporated fully by reference into the present application.

In addition, each of the following U.S. patents and patent applicationsis hereby incorporated by reference in its entirety into the presentapplication:

U.S. Pat. No. 6,649,287, entitled “Gallium Nitride Materials andMethods,” issued on Nov. 18, 2003;

U.S. Pat. No. 7,892,938, entitled “Structure and Method for III-NitrideMonolithic Power IC,” issued on Feb. 22, 2011;

U.S. Pat. No. 7,915,645, entitled “Monolithic Vertically IntegratedComposite Group III-V and Group IV Semiconductor Device and Method forFabricating Same,” issued on Mar. 29, 2011;

U.S. Pat. No. 7,999,288, entitled “High Voltage Durability III-NitrideSemiconductor Device,” issued on Aug. 16, 2011;

U.S. Pat. No. 8,159,003, entitled “III-Nitride Wafer and Devices Formedin a III-Nitride Wafer,” issued on Apr. 17, 2012;

U.S. patent application Ser. No. 13/197,514, entitled “High VoltageIII-Nitride Transistor,” filed on Aug. 3, 2011;

U.S. patent application Ser. No. 13/197,676, entitled “High VoltageDurability III-Nitride HEMT,” filed on Aug. 3, 2011;

U.S. patent application Ser. No. 13/544,829, entitled “CompositeSemiconductor Device With a SOI Substrate Having an Integrated Diode,”filed on Jul. 9, 2012; and

U.S. patent application Ser. No. 13/945,276, entitled “IntegratedIII-Nitride and Silicon Device,” filed on Jul. 18, 2013.

BACKGROUND

I. Definition

As used herein, the phrase “group III-V” refers to a compoundsemiconductor including at least one group III element and at least onegroup V element. By way of example, a group III-V semiconductor may takethe form of a III-Nitride semiconductor. “III-Nitride”, or “III-N”,refers to a compound semiconductor that includes nitrogen and at leastone group III element such as aluminum (Al), gallium (Ga), indium (In),and boron (B), and including but not limited to any of its alloys, suchas aluminum gallium nitride (Al_(x)Ga_((1-x))N), indium gallium nitride(In_(y)Ga_((1-y))N), aluminum indium gallium nitride(Al_(x)In_(y)Ga_((1-x-y))N), gallium arsenide phosphide nitride(GaAs_(a)P_(b)N_((1-a-b))), aluminum indium gallium arsenide phosphidenitride (Al_(x)In_(y)Ga_((1-x-y))As_(a)P_(b)N_((1-a-b))), for example.III-Nitride also refers generally to any polarity including but notlimited to Ga-polar, N-polar, semi-polar, or non-polar crystalorientations. A III-Nitride material may also include either theWurtzitic, Zincblende, or mixed polytypes, and may includesingle-crystal, monocrystalline, polycrystalline, or amorphousstructures. Gallium nitride or GaN, as used herein, refers to aIII-Nitride compound semiconductor wherein the group III element orelements include some or a substantial amount of gallium, but may alsoinclude other group III elements in addition to gallium. A group III-Vor a GaN transistor may also refer to a composite high voltageenhancement mode transistor that is formed by connecting the group III-Vor the GaN transistor in cascode with a lower voltage group IVtransistor.

In addition, as used herein, the phrase “group IV” refers to asemiconductor that includes at least one group IV element such assilicon (Si), germanium (Ge), and carbon (C), and may also includecompound semiconductors such as silicon germanium (SiGe) and siliconcarbide (SiC), for example. Group IV also refers to semiconductormaterials which include more than one layer of group IV elements, ordoping of group IV elements to produce strained group IV materials, andmay also include group IV based composite substrates or siliconcomposite substrates such as silicon on insulator (SOI), separation byimplantation of oxygen (SIMOX) process substrates, and silicon onsapphire (SOS), for example.

II. Background Art

Group III-V semiconductors, such as III-Nitride materials, aresemiconductor compounds that have relatively wide direct bandgaps andcan have strong piezoelectric polarizations, which can enable highbreakdown fields, high saturation velocities, and the creation oftwo-dimensional electron gases (2DEGs). As a result, III-Nitridematerials and other group III-V semiconductors are suitable for use inmany microelectronic applications as field-effect transistors (FETs),including heterostructure FETs (HFETs) such as high electron mobilitytransistors (HEMTs).

Although the III-Nitrides are known as wide bandgap materials, they alsohave relatively high dielectric constants compared to silicon oxide(SiO₂). For example, gallium nitride (GaN) has a dielectric constant ofapproximately 9.5, and aluminum nitride (AlN) has a dielectric constantof approximately 9.1, compared to a dielectric constant of approximately3.9 for SiO₂. As a result, when III-Nitride based FETs are employed forhigh voltage switching applications, the parasitic capacitance acrossthe underlying III-Nitride material layers down to the device substratecan contribute to slower switching times and higher charge for a givenvoltage. Consequently, the increased parasitic capacitance between thedrain or source of the FET and the FET substrate can have undesirableconsequences for its high voltage switching performance.

In the conventional art, the various approaches developed to increasethe breakdown voltage of III-Nitride devices by altering the source anddrain regions in the substrate suffer from other performance drawbacks.One such technique uses locally etched backside substrate removal underthe source and/or drain regions of the III-Nitride devices. Althoughthis technique may increase the breakdown voltage of the device, it canadversely result in the formation of III-Nitride devices with both poorthermal characteristics and unstable surface conditions.

A second technique used is the formation of PN junctions in thesubstrate located under the drain region of the III-Nitride device.However this approach typically leads to leaky PN junctions,particularly at high temperatures, and may also result in relativelyhigh substrate coupling capacitance. Thus, there remains a need for analternative approach to forming III-Nitride power devices which exhibitfast switching times and reduced charge, while maintaining stable highvoltage, high temperature performance, with reduced parasiticcapacitance to the substrate.

SUMMARY

The present disclosure is directed to a semiconductor structureincluding a spatially confined dielectric region, substantially as shownin and/or described in connection with at least one of the figures, andas set forth more completely in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-sectional view of a conventional semiconductorstructure.

FIG. 2 shows a cross-sectional view of an exemplary semiconductorstructure including a spatially confined dielectric region, according toone implementation.

FIG. 3A shows a top view of an exemplary semiconductor structureincluding multiple spatially confined dielectric regions, according toone implementation.

FIG. 3B shows a cross-sectional view of the exemplary semiconductorstructure of FIG. 3A.

FIG. 4 shows a cross-sectional view of an exemplary semiconductorstructure including multiple spatially confined dielectric regions,according to another implementation.

DETAILED DESCRIPTION

The following description contains specific information pertaining toimplementations in the present disclosure. One skilled in the art willrecognize that the present disclosure may be implemented in a mannerdifferent from that specifically discussed herein. The drawings in thepresent application and their accompanying detailed description aredirected to merely exemplary implementations. Unless noted otherwise,like or corresponding elements among the figures may be indicated bylike or corresponding reference numerals. Moreover, the drawings andillustrations in the present application are generally not to scale, andare not intended to correspond to actual relative dimensions.

FIG. 1 shows a cross-sectional view of conventional semiconductorstructure 100. Semiconductor structure 100 includes field-effecttransistor (FET) 120 fabricated over substrate 110. As shown in FIG. 1,FET 120 includes source 132, drain 134, and gate 136. According to theexample shown in FIG. 1, FET 120 is implemented as a III-Nitride FET,such as a III-Nitride high electron mobility transistor (HFET) or othertype of III-Nitride heterostructure FET (HFET) fabricated over substrate110. Substrate 110 may be any type of substrate suitable for use as asupport substrate for FET 120. Thus, substrate 110 may be a group IVsubstrate, such a silicon substrate for example.

As is the case for substantially all HFET structures, there are severalpaths for current flow and leakage across semiconductor structure 100.FIG. 1 shows one such pathway due to the capacitive coupling of drain134 to substrate 110 and labeled as parasitic coupling capacitor 124(C_(III-N)). It is noted that although there may be additional parasiticcapacitances associated with semiconductor structure 100, in manyimplementations, such as when source 132 is tied to substrate 124, thedrain-to-substrate parasitic capacitance represented by parasiticcoupling capacitor 124 is typically of special concern.

As stated above, although the III-Nitride materials are known as widebandgap materials, they also have relatively high dielectric constantscompared to silicon oxide (SiO₂). For example and as also noted above,gallium nitride (GaN) has a dielectric constant of approximately 9.5,and aluminum nitride (AlN) has a dielectric constant of approximately9.1, which may be compared to a dielectric constant of approximately 3.9for SiO₂. When III-Nitride based FETs are employed for high voltageswitching applications, the parasitic capacitance across the underlyingIII-Nitride epitaxial layers of FET 120 down to substrate 110 andrepresented as parasitic coupling capacitor 124, contributes to slowerswitching times and higher switching charge for a given voltage. As aresult, the drain-to-substrate capacitance represented by parasiticcoupling capacitor 124 can have undesirable consequences for the highvoltage switching (speed as well as charge) performance of FET 120.

One conventional method for reducing the parasitic capacitancerepresented by parasitic coupling capacitor 124 is to increase thethickness of the III-Nitride layers used in FET 120. However, in largescale manufacturing of semiconductor switches, large diameter substratesare typically employed. Moreover, the thickness of the III-Nitridelayers formed on large diameter substrates is typically limited by thestresses produced in the III-Nitride material used to form FET 120, aswell as in substrate 110.

The stresses produced in semiconductor structure 100 may be due tomismatch of the lattice constants and/or mismatch of the coefficients ofthermal expansion between the III-Nitride layers used in FET 120 and thesilicon or other typically non-native (i.e., non-III-Nitride) materialsused to provide substrate 110. Those stresses can lead to excessive warpand bow of substrate 110, or to cracking of the III-N layers of FET 120.Consequently, there is a need for an alternative solution for reducingthe parasitic capacitance represented by parasitic coupling capacitor124 that does not require a substantial increase in the thickness of theIII-Nitride layers used to form FET 120 for a given voltage rating. Asnoted above, the use of locally etched substrate regions or theformation of PN junctions in the substrate under the drain regions ofthe III-Nitride FET, as implemented in the conventional art, presentother device performance limitations.

The present application is directed to semiconductor structuresincluding FETs having reduced drain-to-substrate and/or reducedsource-to-substrate capacitive coupling. The solutions disclosed by thepresent application provide FETs having improved high voltage switchingperformance and consequently improved standoff voltage capability, whileconcurrently providing adequate thermal transfer capability between theFET and the substrate. As disclosed herein, such solutions may beachieved through the use of one or more spatially confined dielectricregions formed in the substrate, under the FET drain and/or the FETsource.

Referring to FIG. 2, FIG. 2 shows a cross-sectional view of exemplarysemiconductor structure 200 including spatially confined dielectricregion 240, according to one implementation. Semiconductor structure 200includes FET 220 fabricated over substrate 210. As shown in FIG. 2, FET220 includes source 232, drain 234, and gate 236, and is fabricated overmajor surface 214 of substrate 210. According to the exemplaryimplementation shown in FIG. 2, spatially confined dielectric region 240is formed to a thickness 242 within substrate 210, under drain 234 ofthe FET 220. Also shown in FIG. 2 are III-Nitride parasitic capacitor224 and dielectric parasitic capacitor 244 contributing to thecapacitive coupling of drain 234 to substrate 210 (i.e.,drain-to-substrate capacitive coupling 250), as well as top side 246 ofspatially confined dielectric region 240.

Substrate 210 may be formed using materials such as group IV materials(e.g., Si, SiC, Ge, SiGe, and the like), III-Nitride materials,sapphire, or other suitable material. Substrate 210 may be singlecrystal or polycrystalline, or may be formed as a composite substrate.Moreover, as used in the present application, “silicon substrate” mayrefer to any substrate that includes a silicon surface. Examples ofsuitable silicon substrates include substrates that are formedsubstantially entirely of silicon (e.g., bulk silicon wafers) andsilicon-on-sapphire substrates (SOS) among others. Suitable siliconsubstrates also include composite substrates that have a silicon waferbonded to another material such as diamond, AlN, or otherpolycrystalline materials. In some implementations, silicon substrateshaving different crystallographic orientations may be used. In somecases, for example, silicon (111) substrates may be preferred forsubstrate 210. In other cases, silicon (100) or (110) substrates may bepreferred for substrate 210.

FET 220 may include multiple III-Nitride or other group III-V materiallayers. For example, FET 220 may include one or more III-Nitridetransition layers and/or a buffer layer formed over substrate 210. Inaddition, FET 220 includes at least one active layer. In oneimplementation, for example, FET 220 may be a HEMT including a groupIII-V heterostructure farmed over the transition and/or buffer layersformed over substrate 210. The group III-V heterostructure may include agroup III-V barrier layer formed over a group III-V channel layer andgiving rise to a 2DEG in the group III-V channel layer, as well as oneor more capping and/or passivation layers formed over the group III-Vbarrier layer.

Spatially confined dielectric region 240 may be formed of SiO₂, forexample, and may be formed in substrate 210 through oxygen implantationof substrate 210. For example, oxygen may be implanted into a siliconsubstrate at a concentration of approximately 1×10¹⁸/cm². There areseveral methodologies which may be used to form spatially confineddielectric region 240, including diffusion of oxygen, wafer bonding, andsilicon lateral overgrowth techniques amongst others. However, in someimplementations it may be advantageous or desirable to use separation byimplantation of oxygen (SIMOX).

An SiO₂ spatially confined dielectric region 240 may be formed eitherprior to growth of the III-Nitride epitaxial layers of FET 220 oversubstrate 210, or may be substantially concurrently formed during thegrowth of those III-Nitride epitaxial layers. Thus, in someimplementations, the elevated growth temperatures needed for formationof the III-Nitride epitaxial layers of FET 220 may be utilized to causethe silicon in the vicinity of the implanted oxygen to be consumed,thereby forming SiO₂ spatially confined dielectric region 240. Forexample, spatially confined dielectric region 240 may be located belowmajor surface 214 of silicon substrate 210 such that there is asubstantially uniform layer of silicon at major surface 214, as may berequired for III-Nitride epitaxial nucleation. However, while theIII-Nitride material of FET 220 is being deposited at high temperature,spatially confined dielectric region 240 may grow or expand towardsmajor surface 214 of substrate 210 such that top side 246 of spatiallyconfined dielectric region 240 interfaces with the III-Nitride materialof FET 220.

As shown in FIG. 2, in some implementations, spatially confineddielectric region 240 is substantially centered under drain 234.Moreover, spatially confined dielectric region 240 may by laterallyconfined in a plane substantially parallel to major surface 214 ofsubstrate 210. Spatially confined dielectric region 240 may be a burieddielectric region within substrate 210, or may extend vertically withinsubstrate 210 to major surface 214. In other words, in someimplementations, all sides of spatially confined dielectric region 240may be surrounded by substrate 210, while in other implementations, atop side of spatially confined dielectric region 240 may not be coveredby substrate 210, as shown in FIG. 2.

Although spatially confined dielectric region 240 can be formed of SiO₂,as described above, other dielectrics may also be used. For example, insilicon semiconductor manufacturing, low dielectric constant (low-K)dielectrics have been utilized to reduce parasitic capacitance betweenvarious semiconductor layers. As used herein, a low-K dielectric refersto a dielectric material having a dielectric constant lower than that ofsilicon SiO₂. As noted above, the dielectric constant of SiO₂ isapproximately 3.9. Thus, low-κ dielectrics, such as carbon doped orfluorine doped SiO₂, among other low-K dielectrics, can be used to formspatially confined dielectric region 240.

Thickness 242 of spatially confined dielectric region 240 depends partlyon the voltage range of FET 220. For example, to hold off approximatelyone thousand volts (1,000 V), thickness 242 of a SiO₂ spatially confineddielectric region 240 would be approximately one micrometer (1.0 μm). Invarious implementations, thickness 242 of spatially confined dielectricregion 240 may be in a range from approximately 0.1 μm to approximately3.0 μm.

As further shown in FIG. 2, formation of spatially confined dielectricregion 240 results in an equivalent circuit in which III-Nitrideparasitic capacitor 224 and dielectric parasitic capacitor 244 arecoupled in series between drain 234 of FET 220 and substrate 210.According to the present exemplary implementation, the addition ofdielectric parasitic capacitor 244 in series with III-Nitride parasiticcapacitor 224 advantageously reduces overall drain-to-substratecapacitive coupling 250 for a given voltage. As a result, the presenceof spatially confined dielectric region 240 in substrate 210, and underdrain 234 of FET 220, improves the switching time and charge performanceof FET 220.

It is noted that although the exemplary implementation shown in FIG. 2depicts spatially confined dielectric region 240 as being formed underdrain 234 of FET 220, in other implementations spatially confineddielectric region 240 may be formed under source 232 of FET 220, orunder both drain 234 and source 232 of FET 220. In implementations inwhich spatially confined dielectric region 240 is formed in substrate210 under source 232, spatially confined dielectric region 240 reduces acapacitive coupling of source 232 to substrate 210. Moreover, inimplementations in which spatially confined dielectric region 240 isformed in substrate 210 under both drain 234 and source 232, spatiallyconfined dielectric regions 240 reduces a capacitive coupling of bothdrain 234 and source 232 to substrate 210.

It is further noted that although spatially confined dielectric region240 need not be formed so as only to underlie drain 234 and/or source232 of FET 220, those implementations confer advantages with regard todissipation of heat produced by FET 220. The presence of a burieddielectric material in substrate 210 can have the undesired consequenceof obstructing the thermal path between FET 220, where heat isgenerated, and the bottom of substrate 210, where heat is typicallyextracted. Consequently, use of spatially confined dielectric region240, rather than a continuous dielectric layer, enables the advantagesresulting from reduction of the capacitive coupling of drain 234 and/orsource 232 to substrate 210 described above, while concurrently enablingthe use of conventional thermal management techniques to provideefficient heat management for FET 220.

Continuing to FIGS. 3A and 3B, FIG. 3A shows a top view of exemplarysemiconductor structure 300 including multiple spatially confineddielectric regions 340, while FIG. 3B shows a cross-sectional view ofexemplary semiconductor structure 300. As shown in 3B, semiconductorstructure 300 includes FET 320 fabricated over substrate 310. As shownin FIGS. 3A and 3B, FET 320 includes source regions 332, drain regions334, and gates 336, and is fabricated over major surface 314 ofsubstrate 310. Also shown in FIG. 3 is width 348 of spatially confineddielectric regions 340, and pitch 338 of FET 320, i.e., the distancebetween the centers of immediately adjacent, or neighboring, sourceregions 332. In addition, the width of a drain contact of FET 320 isconceptually represented by interval 335, and the thickness of theIII-Nitride or other group III-V material layers used to produce FET 320is represented as thickness 328, in FIG. 3B.

Although not shown in FIGS. 3A and 3B in the interests of conceptualclarity, it is noted that semiconductor structure 300 may includeadditional overlying layers including passivation and insulating layers,field plates (source, gate, and drain), as well as metal bond pads,traces, and interconnect vias. As shown in FIGS. 3A and 3B spatiallyconfined dielectric regions 340 are centered under respective drainregions 334 and extend laterally toward gates 336 in both directions.FET 320 including source regions 332, drain regions 334, and gates 336corresponds in general to FET 220 including source 232, drain 234, andgate 236, in FIG. 2. Moreover, substrate 310 and spatially confineddielectric regions 340, in FIGS. 3A and 3B, correspond respectively tosubstrate 210 and spatially confined dielectric region 240, in FIG. 2,and may share any of the characteristics attributed to thosecorresponding features above.

It is noted that in some implementations, it may be advantageous ordesirable to determine width 348 of spatially confined dielectricregions 340 based on pitch 338 of FET 320. For example, in oneimplementation, it may be advantageous or desirable to restrict width348 to less then approximately one half (0.5) times pitch 338 of FET320. In other implementations, it may be advantageous or desirable todetermine width 348 of spatially confined dielectric regions 340 basedon thickness 328 of the III-Nitride or other group III-V layer used toform FET 320, as well as on interval 335 corresponding to the width ofthe drain contacts formed on FET 320. For example, it may beadvantageous or desirable to restrict width 348 of spatially confineddielectric regions 340 to less than approximately one or two timesthickness 328, plus interval 335. As a specific example, in variousimplementations, width 348 of spatially confined dielectric regions 340may lie in a range from approximately 5 μm to approximately 30 μm.

Moving to FIG. 4, FIG. 4 shows a cross-sectional view of exemplarysemiconductor structure 400 including multiple spatially confineddielectric regions 440, according to another implementation.Semiconductor structure 400 includes FET 420 fabricated over compositesubstrate 410. As shown in FIG. 4, FET 420 includes source regions 432,drain regions 434, and gates 436, and is fabricated over major surface414 of composite substrate 410. As further shown in FIG. 4, compositesubstrate 410 includes first substrate layer 411 having spatiallyconfined dielectric regions 440 formed therein, and second substratelayer 412 formed over first substrate layer 411 and under FET 420. FET420 including source regions 432, drain regions 434, and gates 436corresponds in general to FET 220 including source 232, drain 234, andgate 236, in FIG. 2. Moreover, spatially confined dielectric regions440, in FIG. 4, correspond to spatially confined dielectric region 240,in FIG. 2, and may share any of the characteristics attributed to thatcorresponding feature above.

Spatially confined dielectric islands or regions 440 may be formed attop surface 418 of first substrate layer 411 of composite substrate 410.Silicon epitaxy with lateral overgrowth may then be used to re-growsilicon on second substrate layer 412 between and above spatiallyconfined dielectric regions 440 and top surface 418 of first substratelayer 411, followed by planarization using standard chemical mechanicalpolishing (CMP) techniques at a top surface of second substrate layer412 to provide major surface 414 of composite substrate 410. In someimplementations, a thin final epitaxial layer of silicon may be grownover the CMP surface to form major surface 414 of composite substrate410 as a III-Nitride ready surface. As a result, and as shown in FIG. 4,in some implementations, all sides of spatially confined dielectricregions 440 may be surrounded by composite substrate 410.

In addition to improving the coupling capacitance of the FET drainand/or source to the substrate, the spatially confined dielectricregions disclosed in the present application can improve the standoffvoltage capability of a FET for a given III-Nitride epitaxial layerthickness. Such a performance improvement results form the fact thatsome portion of the high field regions fall across the spatiallyconfined dielectric regions, which have higher breakdown capability thanthe silicon substrate itself. This has the additional benefit of areduction in the thickness of the III-Nitride epitaxial layer requiredin FET 220 to support a given standoff voltage. Because the presentconcepts permit use of thinner III-Nitride layers to support a givenstandoff voltage, those concepts further enable use of larger diameterwafers for fabrication of FET 220, and/or increased epitaxialthroughput.

Thus the present application discloses semiconductor structuresincluding FETs having reduced drain-to-substrate and/or reducedsource-to-substrate capacitive coupling. As a result, the solutionsdisclosed by the present application provide FETs having improvedstandoff voltage capability and improved high voltage switchingperformance, while concurrently providing adequate thermal transfercapability between the FET and the substrate. As explained above, thepresently disclosed solutions are enabled by formation of one or morespatially confined dielectric regions in the substrate, under the FETdrain and/or the FET source.

From the above description it is manifest that various techniques can beused for implementing the concepts described in the present applicationwithout departing from the scope of those concepts. Moreover, while theconcepts have been described with specific reference to certainimplementations, a person of ordinary skill in the art would recognizethat changes can be made in form and detail without departing from thespirit and the scope of those concepts. As such, the describedimplementations are to be considered in all respects as illustrative andnot restrictive. It should also be understood that the presentapplication is not limited to the particular implementations describedherein, but many rearrangements, modifications, and substitutions arepossible without departing from the scope of the present disclosure.

1. A semiconductor structure comprising: a III-Nitride field-effecttransistor (FET) including a drain, a source, and a gate, fabricatedover a substrate; a spatially confined dielectric region formed undersaid drain in said substrate; said spatially confined dielectric regionreducing a capacitive coupling of said drain to said substrate.
 2. Thesemiconductor structure of claim 1, wherein said spatially confineddielectric region is substantially centered under said drain.
 3. Thesemiconductor structure of claim 1, wherein said spatially confineddielectric region comprises silicon oxide.
 4. The semiconductorstructure of claim 1, wherein said substrate comprises a group IVsemiconductor substrate.
 5. The semiconductor structure of claim 1,wherein said substrate is one of a silicon substrate and a compositesilicon substrate.
 6. The semiconductor structure of claim 1, whereinsaid III-Nitride FET comprises a III-Nitride high electron mobilitytransistor (HEMT).
 7. A semiconductor structure comprising: aIII-Nitride field-effect transistor (FET) including a drain, a source,and a gate, fabricated over a substrate; a spatially confined dielectricregion formed under each of said source and said drain in saidsubstrate; said spatially confined dielectric region reducing acapacitive coupling of said source and said drain to said substrate. 8.The semiconductor structure of claim 7, wherein all sides of saidspatially confined dielectric region are surrounded by said substrate.9. The semiconductor structure of claim 7, wherein a top side of saidspatially confined dielectric region is not covered by said substrate.10. A method comprising: forming a spatially confined dielectric regionin a substrate; fabricating a III-Nitride field-effect transistor (FET)over said substrate, said III-Nitride FET including a drain, a source,and a gate; said drain of said III-Nitride FET being formed over saidspatially confined dielectric region so as to reduce a capacitivecoupling of said drain to said substrate.
 11. The method of claim 10,wherein said spatially confined dielectric region is formed throughoxygen implantation of said substrate.
 12. The method of claim 10,further comprising forming a silicon lateral epitaxial overgrowth layerabove said spatially confined dielectric region and below saidIII-Nitride FET.
 13. The method of claim 10, wherein said spatiallyconfined dielectric region is substantially centered under said drain.14. The method of claim 10, wherein said substrate comprises a group IVsemiconductor substrate.
 15. The method of claim 10, wherein saidsubstrate is one of a silicon substrate and a composite siliconsubstrate.
 16. A method comprising: forming spatially confineddielectric regions in a substrate; fabricating a III-Nitridefield-effect transistor (FET) over said substrate, said III-Nitride FETincluding a drain, a source, and a gate; each of said drain and saidsource of said III-Nitride FET being formed over a respective one ofsaid spatially confined dielectric regions so as to reduce a capacitivecoupling of said drain and said source to said substrate.
 17. The methodof claim 16, wherein said spatially confined dielectric regions areformed through oxygen implantation of said substrate.
 18. The method ofclaim 16, further comprising forming a silicon lateral epitaxialovergrowth layer above said spatially confined dielectric regions andbelow said III-Nitride FET.
 19. The method of claim 16, wherein saidsubstrate comprises a group IV semiconductor substrate.
 20. The methodof claim 16, wherein said substrate is one of a silicon substrate and acomposite silicon substrate.